The present invention relates to memory management, and more specifically, to double data rate (DDR) memory read latency reduction.
In a typical memory buffer design read data from synchronous dynamic random-access memory (DRAM) is gated into a memory interface first-in-first-out (FIFO) governed by the timing of the incoming strobes. The data must then be read out of this FIFO for delivery to the host requestor. If the memory interface resides on a disparate memory buffer chip which is connected to the host via a serializer/deserializer (SERDES) interface, then an intermediate data transfer from the memory interface FIFO to the SERDES FIFO is required to serialize the data for transmission on the host channel. These transfers require crossing two, and sometimes three, distinct clock boundaries thereby introducing additional latency in the data return path due to non-optimal clock alignment between the boundaries. Sometimes this additional latency amounts to several memory clock cycles, which can have an appreciable performance impact on read accesses.